High dynamic range low ripple RSSI for zero-IF or low-IF receivers

ABSTRACT

A received signal strength indicator operating at low intermediate of zero intermediate frequency is provided. The received signal strength indicator forms absolute values from an in-phase signal component and a quadrature signal component of a low or zero intermediate frequency signal that represents a received radio frequency signal. The absolute values are added. Logarithmic signal processing is performed either before absolute signal forming or after adding. Finally, low pass filtering is performed.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a received signal strengthindicator for a zero intermediate frequency or a low intermediatefrequency radio device such as a receiver or transceiver. Such a radiodevice receives radio frequency signals, and, when a transmit part isalso present, also transmits signals. Such a radio device can be acellular radio device, a cordless telephone, a wireless local areanetwork radio device, a satellite radio device, or any other suitableradio device.

[0003] 2. Description of the Related Art

[0004] In the U.S. Pat. No. 5,603,112, a received signal strengthindicator is disclosed. The received signal strength indicator is usedfor performing signal strength measurements of received radio frequencysignals in radio frequency receivers. The received signal strengthindicator comprises analog to digital converters for sampling quadraturedown modulated signals at an intermediate frequency. Output signals ofthe analog to digital converters are supplied to respective comparatorsthat compare magnitudes of the quadrature intermediate frequencysignals. Based on comparison results, the magnitudes of either thein-phase signal or quadrature signal is supplied to either adivide-by-16 divider, to a divide-by-8 divider, or by a divide-by-4divider. The in-phase and quadrature signals, and the divided in-phaseand quadrature signals are combined in a number of adders, one of theadders providing the received signal strength indicator signal. Throughsuch a comparison, division, and combining, a scaled combination ofapproximated magnitudes of in-phase and quadrature down convertedquadrature signals is computed, approximating the magnitude of thereceived vector, the received vector being the square root of the sum ofthe squared magnitudes of the in-phase and quadrature down convertedquadrature signals. Such a computation of an approximation of themagnitude of the received vector, used as a received signal strengthindicator signal in the intermediate frequency domain, is complex.

[0005] In the U.S. Pat. No. 5,338,985, a received signal strengthindicator for operation at intermediate frequencies is disclosed. Thereceived signal strength indicator comprises a number of cascadedamplifiers that amplify an intermediate frequency signal. Output signalsof the respective amplifiers are rectified, and, after voltage tocurrent conversion, currents representing rectified signals areweightedly added so as to obtain a received signal strength indicatorsignal. From the last amplifier of the multistage amplifier to the firstamplifier, the amplifiers successively run out of their linear regionand get into their limiting or clipping range, with an increasing inputsignal amplitude. Herewith, the resulting received signal strengthindicator signal approximates a linear function of the logarithm of theinput intermediate frequency signal. The more amplifier stages in thecascade of amplifiers, the better the linear approximation is.

[0006] In the U.S. Pat. No. 5,978,664, peak detector is disclosed. Thepeak detector is particularly suitable for measuring the peak value ofan RSSI signal formed by a multistage limiting and summing logarithmicamplifier. Reducing a ripple in a combination of a multistage limitingand summing logarithmic amplifier and peak detector, desirable to get amore reliable received signal strength indicator signal, renders thetime response of the combination worse, i.e., the signal undesirablyslowly decays after a sudden change in the amplitude of the highlydynamic radio signal to be measured.

[0007] On page 62 of the DRAFT Supplement, Part 11, of the IEEE 802.11bstandard, operating channels are shown for North American Channelselection in the so-called 2.4 GHz ISM band.

SUMMARY OF THE INVENTION

[0008] It is an object of the invention to provide a received signalstrength indicator signal at zero intermediate frequency or lowintermediate frequency that is simple, that is low ripple, and that hasa high dynamic range.

[0009] It is another object of the invention to provide a receivedsignal strength indicator that produces a received signal strengthindicator signal approximating a linear function of the logarithm of aninput signal supplied to the received signal strength indicator.

[0010] It is still another object of the invention to provide a receivedsignal strength indicator wherein for a particular modulation type ofsignals, such as QPSK, signal glitches are avoided.

[0011] In accordance with the invention, a method of determining areceived signal strength indicator signal from an in-phase signalcomponent and a quadrature signal component of a low intermediatefrequency signal that represents a received radio frequency signal, isprovided comprising:

[0012] determining a first absolute value from said in-phase signalcomponent;

[0013] determining a second absolute value from said quadrature signalcomponent; and

[0014] summing said first and second absolute values.

[0015] The approximately linear function of the logarithm of the inputsignal is obtained by logarithmically processing of signals, eitherbefore or after determining the first and second absolute values.

[0016] Preferably, logarithmic processing is performed beforedetermining the first and second absolute values, by a multistagelimiter followed by an adder for adding signals produced by the limiter,in both the in-phase and quadrature signal path.

[0017] By low pass filtering the added absolute values, signal glitchesare avoided.

BRIEF DESCRIPTION OF THE DRAWING

[0018]FIG. 1 schematically shows a block diagram of a transceiver with areceived signal strength indicator according to the invention.

[0019]FIG. 2 shows a first embodiment of a received signal strengthindicator according to the invention.

[0020]FIG. 3 shows a second embodiment of a received signal strengthindicator according to the invention.

[0021]FIG. 4 shows an absolute signal former.

[0022]FIG. 5 shows an adder.

[0023]FIG. 6 shows a multistage limiter and adder.

[0024] Throughout the figures the same reference numerals are used forthe same features.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0025]FIG. 1 shows a block diagram of a transceiver 1 as a zerointermediate frequency or low intermediate frequency radio device. Sucha radio device can be a time division duplex radio device operating inthe so-called 2.4 GHz ISM band, accordance with said IEEE 802.11bstandard, or any other suitable radio device. The transceiver 1comprises a receive branch Rx and a transmit branch Tx. In anotherembodiment in which no transmit branch Tx is present, the radio deviceis a receiver only. The transmit branch Tx comprises a quadrature mixercomprised of filters 2 and 3, mixers 4 and 5, and an adder 6. The adder6 is coupled to a power amplifier 7. The power amplifier 7 is coupled toan Rx/Tx-switch 8. The Rx/Tx-switch 8 is coupled to an antenna 9.Quadrature transmit signals Tx_I and Tx_Q are generated by a modulator(not shown), and supplied to the filters 2 and 3, respectively. Thereceive branch Rx comprises a low noise radio frequency amplifier (LNA)10 that is coupled to the Rx/Tx-switch 8. The LNA 10 amplifies a radiofrequency signal RF that is received by the antenna 9. The receivebranch Rx further comprises a quadrature down converter that comprisesmixers 11 and 12 and channel filters 13 and 14. The transceiver 1further comprises a frequency synthesizer 15 that generates quadraturelocal oscillator signals LO_I and LO_Q. The signal LO_I is supplied tothe mixers 4 and 11. The signal LO_Q is supplied to the mixers 5 and 12.If the transceiver 1 is a zero intermediate frequency radio deviceoperating in the ISM band, and receiving and transmitting in channel oneof the ISM band, the frequency synthesizer 15 is tuned to 2.4 GHz. Ifthe transceiver 1 is a low intermediate frequency radio device operatingin the same band and channel, the frequency synthesizer is tuned to aslightly different frequency than 2.4 GHz. The transceiver 1 furthercomprises a base band circuit 16 with analog to digital converters 17and 18 for processing down converted quadrature signals Rx_I and Rx_Q,and with a processor 19. The processor 19 comprises non-volatile memory(not shown) with a stored program, and volatile memory (not shown) forstoring temporary data. The transceiver 1 further comprises a receivedsignal strength indicator circuit 20 according to the invention thatprovides a received signal strength indicator signal RSSI. The signalRSSI is a high dynamic range low ripple signal, at zero-IF or at low IFthat resolves the dynamic high range of the received radio frequencysignal RF. In a radio device operating in the ISM band, the dynamicrange typically is 80 dB. The signal RSSI can be used for controllingfunctions in the transceiver 1, or to provide signal strengthinformation to a system in which the transceiver operates. The RSSIcircuit 20 can be implemented in conventional digital hardwaretechnology, or as a so-called ASIC (Application Specific IntegratedCircuit), or as a programmed processor, or any other suitableimplementation. In case the RSSI circuit 20 is implemented as aprogrammed processor, in addition to demodulating sampled signals Rx_Iand Rx_Q, the processor performs a computational function to compute thesignal RSSI. If needed for analog control function in the transceiver 1,a computed signal RSSI is supplied to a digital to analog converter.

[0026]FIG. 2 shows a first embodiment of the received signal strengthindicator (RSSI) 20 according to the invention. The RSSI 20 comprises alimiter and summer 30 to which the signal Rx_I is supplied, and alimiter and summer 31 to which the signal Rx_Q is supplied. Limited andsummed signals are supplied to respective absolute signal formers 32 and33. Absolute signals are added by an adder 34. Added absolute signalsare low pass filtered by low pass filter 35. The low pass filterprovides the RSSI signal.

[0027]FIG. 3 shows a second embodiment of the received signal strengthindicator 20 according to the invention. The RSSI 20 comprises absolutesignal formers 40 and 41 to which the respective signals Rx_I and Rx_Qare supplied, and further an adder 42 for adding absolute signals. Theadder 42 is coupled to a logarithmic signal former 43. The logarithmicsignal former 43 is coupled a low pass filter 44 providing the RSSIsignal.

[0028]FIG. 4 shows an absolute signal former comprised of a hard limiter50 and a multiplier 51. The hard limiter 50 can be a high gainamplifier. A signal V_(IN) appears at the output as a signal ABS(V_(IN)).

[0029]FIG. 5 shows an adder comprised of an operational amplifier 60with resistors R to provide input signals V₁, V₂, and V₃ to the opamp60, and a feedback resistor R_(f). An output signal of the opamp isVOUT=−R_(f)/R.(ΣV_(i)), i=1, 2, 3.

[0030]FIG. 6 shows a multistage limiter and adder comprised of a cascadeof differential amplifiers 70 and 71, further differential amplifierstages being indicated by a dashed line. The number of stages is six,for instance. The stage 70 comprises transistors 72 and 73 to which aninput signal V_(i) is supplied. Further shown is a load resistor RL.Similarly, the stage 71 comprises transistors 74 and 75. The signalV_(i) is supplied to all stages. Through an adder 76, a log limitedsignal is formed from the amplified signals V_(i).

[0031] In view of the foregoing it will be evident to a person skilledin the art that various modifications may be made within the spirit andscope of the invention as hereinafter defined by the appended claims andthat the invention is thus not limited to the examples provided. Theword “comprising” does not exclude the presence of other elements orsteps than those listed in a claim.

What is claimed is:
 1. A method of determining a received signalstrength indicator signal from an in-phase signal component and aquadrature signal component of a low intermediate frequency signal thatrepresents a received radio frequency signal, said method comprising:determining a first absolute value from said in-phase signal component;determining a second absolute value from said quadrature signalcomponent; and summing said first and second absolute values.
 2. Amethod as claimed in claim 1, further comprising logarithmicallyprocessing said in-phase and quadrature signal components beforedetermining said first and second absolute values.
 3. A method asclaimed in claim 2, wherein said logarithmically processing comprisesmultistage limiting of said in-phase and quadrature signal components,and summing said multistage limited in-phase and quadrature signalcomponents.
 4. A method as claimed in claim 1, further comprisinglogarithmically processing said in-phase and quadrature signalcomponents after summing said first and second absolute values.
 5. Amethod as claimed in claim 1, wherein said received signal strengthindicator signal is further determined by low pass filtering said summedfirst and second absolute values.
 6. A method as claimed in claim 1,wherein said low intermediate frequency signal is a zero intermediatefrequency signal.
 7. A radio device comprising: an antenna for receivinga radio frequency signal; a quadrature down converter for producing alow intermediate frequency in-phase signal component and a lowintermediate frequency quadrature signal component from said radiofrequency signal; a received signal strength indicator for producing areceived signal strength indicator signal from said low intermediatefrequency in-phase and quadrature signal components, said receivedsignal strength indicator comprising a first absolute value former forderiving a first absolute signal from said in-phase signal component, asecond absolute value former for deriving a second absolute signal fromsaid quadrature signal component, and an adder for adding said first andsecond absolute signals.
 8. A radio device as claimed in claim 7,wherein said received signal strength indicator further comprises afirst logarithmic signal former for determining a first logarithmicsignal from said in-phase signal component and a second logarithmicsignal former for determining a second logarithmic signal from saidquadrature signal component, said first absolute signal being said firstlogarithmic signal and said second absolute signal being said secondlogarithmic signal.
 9. A radio device as claimed in claim 8, whereinsaid first and second logarithmic signal formers comprise respectivemultistage limiters and respective adders for adding signals produced bysaid multistage limiters.
 10. A radio device as claimed in claim 7,wherein said received signal strength indicator further comprises a lowpass filter for low pass filtering said added first and second absolutesignals.
 11. A radio device as claimed in claim 7, wherein said lowintermediate frequency signal is a zero intermediate frequency.
 12. Aradio device as claimed in claim 7, wherein said received signalstrength indicator further comprises a logarithmic signal former forforming a logarithmic signal from said added first and second absolutesignals.
 13. A received signal strength indicator for use in radiodevice with an antenna for receiving a radio frequency signal, aquadrature down converter for producing a low intermediate frequencyin-phase signal component and a low intermediate frequency quadraturesignal component from said radio frequency signal, and said receivedsignal strength indicator for producing a received signal strengthindicator signal from said low intermediate frequency in-phase andquadrature signal components, said received signal strength indicatorcomprising a first absolute value former for deriving a first absolutesignal from said in-phase signal component; a second absolute valueformer for deriving a second absolute signal from said quadrature signalcomponent; and an adder for adding said first and second absolutesignals.
 14. A received signal strength indicator as claimed in claim14, wherein said low intermediate frequency signal is a zerointermediate frequency signal.